1. Field
The invention relates to a method for fabricating transistors of different conduction types arranged in a first section of a surface of a semiconductor substrate with a high packing density and in a second section with a low packing density.
2. Background Information
New generations of DRAM (Dynamic Random Access Memory) modules for storing data in data processing devices are required to have, in conjunction with smaller dimensions, a higher number of memory cells and thus an increasing storage density. A memory cell in each case comprises a storage capacitance for storing an electrical charge that defines a respective data content of the memory cell, and a selection transistor for selectively addressing the storage capacitance.
A high storage density requires memory cells with self-aligning contacts. Self-aligning contacts are customarily embodied by encapsulating gate electrodes of the selection transistors with a dielectric before the formation of the self-aligning contacts.
One example of such a process implementation is illustrated in FIG. 1. In this case, a first dielectric layer 11, from which a gate dielectric emerges, is provided on a semiconductor substrate 10, and an n-doped gate electrode layer 12 is provided on the first dielectric layer 11. The n-doped gate electrode layer 12 is provided with a contact layer 15.
FIG. 1a shows a resultant layer stack with the contact layer 15 arranged on the gate electrode layer 12, which contact layer may comprise a silicide layer, or a metal layer in connection with a barrier layer. The first dielectric layer 11 serving as a gate dielectric is formed between the gate electrode layer 12 and the semiconductor substrate 10.
A dielectric layer used as a hard mask is subsequently deposited onto the layer stack. Afterward, the layer stack is patterned by means of a lithographic method. Gate structures 5 assigned to a respective transistor are produced. The gate structures 5 are encapsulated with a second dielectric layer 16.
FIG. 1b illustrates a plurality of gate structures 5. Gate electrodes 7 have emerged from the gate electrode layer 12, said gate electrodes in each case being provided with a contact layer 15. The gate structures 5 are in each case encapsulated with a second dielectric layer 16. In a first section 1 of the semiconductor substrate 10, in which a memory area of a DRAM module is formed, the gate structures 5 are arranged closely adjacent with a high packing density and are to be assigned to transistors 3 formed as selection transistors of memory cells. In a second section 2, the gate structures 5 are arranged at a greater distance from one another with a high packing density and are assigned to transistors 5, 5′ of logic circuits, for instance for signal conditioning and addressing.
FIG. 1c illustrates, in the second section 2, n-conducting transistors 3 after an n-doping of respectively assigned source/drain regions 6 and p-conducting transistors 3′ after a p-doping of assigned source/drain regions 6′.
With this type of process implementation, the way in which the gate electrodes are fabricated is disadvantageous because it has the effect that the gate electrodes always have the same doping type irrespective of a conduction type of the transistor. Thus the example of FIG. 1 provides both n-conducting and p-conducting transistors with n-doped gate electrodes. What is disadvantageous about such a transistor type is a poor scalability and a lower performance compared with a p-conducting transistor with a p-doped gate electrode.
Thus, the so-called DWF (Dual Work Function) process, which is customary for pure logic circuits and in which source/drain regions and gate electrode of a transistor are simultaneously doped with the same dopant, cannot be integrated in the case of the conventional process implementation. For such a DWF process, the gate electrode should be uncovered at the time when the source/drain regions are doped.
A further disadvantage of the encapsulated gate structures results from the fact that it is not possible to carry out a self-aligning siliciding process (SALICIDE, Self-aligned Salicide Process) which is customary for logic circuits and in which the source/drain regions and the gate electrode of a transistor are provided with a self-aligning silicide layer for the purpose of reducing the nonreactive resistance at the contact points. In the case of a transistor for a logic circuit with high performance, the gate electrodes are not permitted to be encapsulated during the siliciding. However, dispensing with encapsulated gate electrodes makes it more difficult to effect the self-aligning contact-connection in the memory area and thus to realize a high storage density. Thus, it is possible to fabricate either DRAM modules with a high storage density and with logic circuits whose performance is restricted or else DRAM modules with logic circuits having a high performance but a low storage density.
One possibility for avoiding the disadvantages of a common processing of logic area and memory area is described in U.S. Pat. No. 6,287,913. In this case, logic area and memory area are processed independently of one another. Firstly the memory area is processed and subsequently provided with a protective layer. The logic area is then processed. However, this procedure requires almost twice the number of process steps compared with the processing described in the introduction. Therefore, this is expensive and time-consuming.